Layout / Backend

Soft-Mastrer Physical design, Layout and Backend teams carry out SoC from RTL to GDS. We provide full backend services using the most cutting edge EDA tools and methodologies. We have extensive experience in implementing complex designs with high clock frequencies. Our customers include global silicon companies with the most advanced CMOS processes.

We deliver high-performance SoC designs that combine proven low-power design flow with aggressive power and clock gating. Our engineers achieve high design quality for the most complex low power consumption use cases by leveraging:

low noise design technology
high-accuracy analysis technology
high-performance synthesis, placement, routing, and high-speed technology
power optimized microarchitecture and cutting-edge CMOS process technologies

Our Services

Clock and reset architectures
DFT - Design for test of all logic, Memories, Analog IP, High-Speed I/O and SerDes
RTL-to-gate level netlist Synthesis
Hierarchical timing budgeting and floor plan design
Hierarchical power budgeting and power grid design
Qualifying libraries, existing netlist vs. RTL and design constraints
Timing and SI-aware place and route
Full-chip RC extraction
Full-chip timing/SI closure, static timing analysis and sign-off
Full-chip physical verification (DRC)
Signal Integrity
GDSII Generation